Japanese Patent Application Laid-open Publication No. 2010-147405 (Patent Document 1) describes a technique to achieve both improvement of a break-down voltage and reduction in an on-resistance in a normally off type junction FET. Specifically, the Patent Document describes a technique in a junction FET using silicon carbide as a substrate material, the technique introducing an impurity into the vicinity of a p-n junction between a gate region and a channel formation region, the impurity having a reverse conductivity type against an impurity introduced in the gate region but the same conductivity type as an impurity introduced in the channel formation region.